ELEC70287 DES project  Sem1 2017/18
FSM Design and Simulation
Aims and Objectives

For ALL of the state machines specified below create a state diagram and use VHDL to synthesise the required logic circuit.

Enter your designs as a project in Xilinx ISE and construct a VHDL testbench to show that your circuit operates correctly.

Note that there is more than one possible solution to each problem that will provide a correct result!


Deliverables

For the three circuits you should provide a word file containing :

· state diagram created from the specification

· evidence of your design process

· a copy of the design and  associated testbench(.VHD files)

· evidence of the simulator output from Xilinx.

These should be contained in a single word document or PDF.

Submit your file via Blackboard.

The deadline is 23:59 on FRIDAY 12th Jan 2018





Circuit 1 – Simple 2 bit up/down counter with asynchronous reset

Design a 2 bit counter with a control input C that counts UP in binary when C=0 and DOWN when C=1.  Provide an asynchronous reset input to zero the counter.


Circuit 2 – 4 bit Binary/BCD Counter with Overflow

Design a state machine that counts up in binary from 0 to 15 when the control input is a ‘1’ and  in BCD  sequence (0-9 in binary )when the control input is a ‘0’.

An additional output should be provided that is active (=1) when the counter ‘rolls over’ to start the next sequence  (i.e. in state “0”).

0000,0001,0010,0011,0100,0101,0110,0111, 1000,1001,1010,1011,1100,1101,1110,1111 – BINARY Sequence

0000,0001,0010,0011,0100,0101,0110,0111, 1000,1001 – BCD sequence


Circuit 3 –Timing delay Module

Design a state machine that will create a fixed length delay (monostable). The delay should be started by an input signal (START) being equal to 1 and the end of the delay (10000 clock cycles) should be indicated by the output (FINISH) being asserted.

Your design should ensure that the FINISH signal is only asserted for ONE clock cycle and that the counter is then paused/disabled so that the comparison cannot occur again until the delay has been re-triggered by the START signal.


Marking Scheme
The marks for your design are allocated as follows:

o Completion of Design process /20

o Xilinx Design Entry /30

o Isim and Testbench use /30

o Interpretation of simulation results /20

This total will be multiplied by the difficulty rating for the chosen circuit.